Some integrated circuits such as a micro-controller have a built-in CR oscillating circuit (or ring oscillator) on a chip, and a clock signal for the micro-controller is supplied from the built-in oscillating circuit. This is because in the case of an oscillating circuit using a crystal resonator or ceramic resonator, the start-up time which means the time from power is turned on until the output frequency of the oscillating circuit stabilizes is long, and it is sometimes desirable to use a CR oscillating circuit, a ring oscillator, or the like having a shorter start-up time as a clock source, even with a decrease in the accuracy of oscillation frequency. More specifically, for applications that frequently repeat starting and stopping of an oscillating circuit, a waiting time occurs at the start-up of the oscillating circuit, and it is sometimes desirable from the viewpoint of overall system performance improvement to reduce the power consumption during this waiting time. Also, an on-chip oscillating circuit is sometimes used for the purpose of cost reduction as well.
FIG. 1 is a circuit diagram of a CR oscillating circuit. In the CR oscillating circuit, IV1, IV2, and IV3 each denote an inverter, C1 and C2 each denote a capacitor, R1 denotes a resistor, ND1 to ND4 each denote a node within the oscillating circuit, and GND denotes a ground potential (0 V). The waveform of each of the nodes ND1, ND2, and ND3 is the output waveform (rectangular wave) of a CMOS circuit. The waveform of the node ND4 is such that owing to capacitive coupling between the nodes ND2 and ND4, at the time of a potential change of the node ND2, the potential of the node ND4 changes in the same direction as the node ND2, and is thereafter gradually charged/discharged by the potential of the node ND3 and the resistor R1.
FIG. 2 is a circuit diagram of another oscillating circuit. In FIG. 2, IV1 and IV4 each denote an inverter, C1 and C2 each denote a capacitor, NMn (n is an integer) denotes an N-channel MOS transistor, and PMn (n is an integer) denotes a P-channel MOS transistor. In FIG. 2, Vdd denotes a positive power supply voltage (for example, 3 V), GND denotes a ground potential (0 V), NDn (n is an integer) denotes a node within the oscillating circuit, VBGR denotes a constant voltage (for example, 2 V) generated from a band gap circuit, PB denotes the bias potential of a P-channel MOS transistor PM1, and NB denotes the bias potential of an N-channel MOS transistor NM2.
In the circuit illustrated in FIG. 2, nodes and elements corresponding to those of the circuit illustrated in FIG. 1 are assigned the same symbols to make their correspondence clear. In the circuit illustrated in FIG. 2, a node ND5 at one end of the capacitor C1 is driven by an inverter (transistors PM3 and NM3) with the constant voltage VBGR as the power supply, thereby controlling the signal amplitude of the node ND5 to be constant irrespective of temperature. In order to achieve a design in which frequency is independent of temperature, the circuit is so configured as to make the current flowing through transistors PM2 and NM1 constant independent of temperature. The bias potentials PB and NB are such potentials that make the current flowing through the transistors PM2 and NM1 constant.
The bias generation circuitry for generating the bias potentials PB and NB is all integrated on a semiconductor chip, and the circuit configuration as described below is adopted to generate a temperature-independent current. To generate a constant current, the potential generated by flowing a current through a resistor, and a reference voltage are made to coincide with each other by feedback control. By taking the temperature dependence of an on-chip resistor into account, temperature dependence is imparted to the reference voltage. The circuit is designed so that by imparting a positive temperature dependence to the reference voltage such that as the resistance becomes larger with a rise in temperature, the reference voltage also becomes larger with temperature, the temperature dependence of the resistor is cancelled out by the temperature dependence of the reference voltage, thereby ensuring that current is independent of temperature. The above-mentioned circuit realizes an oscillating circuit whose oscillation frequency is constant with respect to temperature and power supply voltage.
Although the circuit illustrated in FIG. 1 succeeds in achieving an oscillation frequency that is independent of power supply voltage by use of the capacitors C1 and C2 and the resistor R1, the circuit has a drawback in that if the resistor R1 is dependent on temperature, it is difficult to suppress fluctuation of oscillation frequency. In the case where the resistor R1 is integrated into a semiconductor chip, for example, it is practically difficult to reduce the temperature dependence of the resistor R1 below a certain level. Also, when the values of the resistor R1 and capacitors C1 and C2 fluctuate owing to manufacturing variations, so does oscillation frequency. That is, the circuit illustrated in FIG. 1 has the following problems: when the values of the resistor R1 and capacitors C1 and C2 fluctuate owing to manufacturing variations, oscillation frequency also fluctuates; and when the value of the resistor R1 varies owing to temperature fluctuation, oscillation frequency fluctuates.
The circuit illustrated in FIG. 2 aims to cancel out the temperature dependence of a resistor by the temperature dependence of a pre-designed built-in reference voltage, and generate the bias potentials PB and NB for charging/discharging the capacitors C1 and C2 at constant current, thereby mitigating temperature variation of oscillation frequency. However, an error is present in the actual output potential VBGR of a reference voltage generation circuit. This error also causes the temperature dependence of the potential VBGR to become slightly positive or negative depending on each individual circuit manufactured. Even more ideally, even when the circuit is configured so as to make the current flowing through the transistors PM2 and NM1 constant independent of temperature, because an error is also present in this portion, the temperature dependence of the charging/discharging current for the capacitors C1 and C2 does not become exactly the same as a designed value, either. Furthermore, the delay time of the inverters IV1 and IV4 is also dependent on temperature and each individual circuit manufactured, and thus becomes the cause of an error in the temperature characteristics of oscillation frequency.
In the circuit illustrated in FIG. 2, even if it is attempted to control the current that charges the capacitors C1 and C2 to be constant by means of the bias potentials PB and NB, when the node ND4 changes from low level to high level, the transistor NM1 turns OFF, so the drain potential of the transistor NM2 becomes the ground potential GND. Since a parasitic capacitance is present at the drain of the transistor NM2, when the node ND4 changes from high level to low level, the discharging current for the node ND4 does not become exactly the same as the current set by the bias potential NB. An extra electrical charge equivalent to the parasitic capacitance at the drain of the transistor NM2 being charged from the ground potential GND to a given potential is discharged from the node ND4. Likewise, the parasitic capacitance at the drain of the transistor PM1 also becomes the cause of an error in the setting of current.
Japanese Laid-open Patent Publication No. 63-304702 discloses an oscillating circuit configured so that, in a ring oscillator in which a plurality of stages of gates are serially connected and the gate output of the last stage is fed back to the gate input of the first stage to thereby excite oscillation, a transfer gate is inserted in between adjacent gates, and the transfer gate is connected to a control potential that may be made variable in an analog manner.